Sample: Analyzing the ColdFire 5307

   The ColdFire family of microcontrollers is the successor of the well known M68k architecture of Motorola. The ColdFire 5307 is an implementation of the Version 3 ColdFire architecture. It contains an on-chip 4K SRAM, a unified 8K data/instruction cache, and a number of integrated peripherals.

   It implements a subset of the M68k opcodes, restricting opcodes to two, four or six bytes, thereby simplifying the decoding hardware. The CPU core and the external memory bus can be clocked with different speeds (e.g. 20MHz bus clock and 60MHz internal core clock).


   In the IST project DAEDALUS, we developed and implemented a complete WCET analysis for the MCF 5307, consisting of a value analysis, an integrated cache and pipeline analysis and a path analysis. In addition to the raw information about the WCET, several parts can be visualized by the graph layout software aiSee to view detailed information delivered by the analysis.

aiSee Graph Layout Software

   The WCET system for the Motorola ColdFire MCF5307 processor was designed according to the requirements of AIRBUS France for validating the timing behavior of critical avionics software. The WCET analyzer has been installed in AIRBUS Toulouse plant.

   ''The results obtained on this topic [WCET], and the improvements of the AbsInt tool is one of the most important results of the DAEDALUS project, from both technical and industrial points of view. [...] The AbsInt tool is probably the best of its kind in the world, and it is justified to consider this result as a breakthrough.'' 
DAEDALUS Project Final Review

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